Search - verilog cpu

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[VHDL-FPGA-Verilog] 32bit-RISC-CPU-IP DL : 1: 使用Verilog语言实现的RISC精简指令集CPU IP核，该CPU具有32位数据宽度，5级流水线结构和指令预判和中断处理功能，适合Verilog语言深入学习者参考。-Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction pre-judgment and interrupt handling functions for Verilog language learners in depth reference.
Date : 2025-07-06 Size : 33kb User : 张秋光
[VHDL-FPGA-Verilog] Digital-Design-Through-Verilog DL : 0: cpu design an intutive approach raja sekhar 08-12
Date : 2025-07-06 Size : 1.64mb User : raja
[VHDL-FPGA-Verilog] CPU-32 DL : 0: A 32 bit cpu implementation designed on verilog with test bench.
Date : 2025-07-06 Size : 5kb User : zi
[VHDL-FPGA-Verilog] lab13 DL : 0: Quartus实现单周期处理器，利用verilog语言-verilog cpu design
Date : 2025-07-06 Size : 885kb User : chengshanbo
[Software Engineering] mips--cpu DL : 0: 本文基于32位 MIPS CPU的体系架构，采用Xilinx ISE 9.1i软件，通过使用Verilog语言编写了32位MIPS单周期和多周期CPU的程序，完成了其逻辑设计并进行了仿真测试。-Based on a 32 MIPS CPU architectures using the Xilinx ISE 9.1i software, write a 32-MIPS, single cycle and multi-cycle CPU program completed its logic design and simulation tests using the Verilog language.
Date : 2025-07-06 Size : 307kb User : 朱祖建
[VHDL-FPGA-Verilog] RISC-CPU DL : 1: 用FPGA实现一个简易的CPU，采用精简指令集结构，每一条指令有16bit，高三位为指令操作数，后13位为地址，该CPU能实现8种指令操作，分别有HLT（空一个中期）ADD（相加操作）SKZ（为零跳过）AND（相与操作）XOR（异或操作）LDA（读数据）STO（写数据）JMP（无条件跳转指令）。cpu包括8个部件，分别为时钟发生器、指令寄存器、累加器、算术逻辑单元、数据控制器、状态控制器、程序计数器、地址多路器，各个部件之间的相互操作关系由状态控制器来控制，程序指令存放在初始rom中，本例程存放在存储器初始文件中。 PS：为什么没有Verilog选项呢-A simple CPU, FPGA implementation to streamline the instruction set architecture, each instruction 16bit, high three operands for the instruction, the 13 address, the CPU can achieve the eight kinds of instruction operations, respectively, HLT (a medium-term empty) ADD (add operation) SKZ (zero skip) AND (phase operation) the XOR (exclusive OR operation) LDA (read data) STO (write data) JMP (unconditional jump instruction). cpu consists of eight parts, clock generator, the instruction register, accumulator, arithmetic logic unit, the data controller, the state controller, the program counter, the address multiplexer, the various components interoperate relations by the state controller to control, program instructions stored in the initial rom the routines stored in memory the initial file. PS: Why is there no Verilog options.
Date : 2025-07-06 Size : 3mb User : vice
[Other] single-clock-CPU DL : 0: 单时钟周期CPU，verilog语言编写，quartusII运行-A single clock cycle CPU
Date : 2025-07-06 Size : 2.01mb User : 周骁
[ARM-PowerPC-ColdFire-MIPS] ARM-Verilog-HDL-IP-CORE DL : 0: ARM处理器的IP核，用verilog编写的，对处理器和相关的CPU架构知识有很大帮助。-ARM processor IP core, written in verilog processor and CPU architecture knowledge.
Date : 2025-07-06 Size : 73kb User : shen jun
[VHDL-FPGA-Verilog] cpu DL : 0: 用verilog语言写的简单cpu，在处理器功能和结构上，对于初学者有很大帮助。-Verilog language write simple cpu, processor function and structure of great help for beginners.
Date : 2025-07-06 Size : 15kb User : shen jun
[Other] Verilog DL : 0: 程序员利用一种由专家设计的既可以被人理解，也可以被计算机解释的语言来表示算法问题的求解过程。这种语言就是编程语言。由它所表达的算法问题的求解过程就是程序。我们已经熟悉通过编写程序来解决计算问题， C、Pascal、Fortran、Basic 或汇编语言语言是几种常用的编程语言。如果我们只研究算法，只在通用的计算机上运行程序或利用通用的CPU 来设计专用的微处理器嵌入系统，掌握上述语言就足够了。如果还需要设计和制造能进行快速计算的硬线逻辑专用电路，我们必须学习数字电路的基本知识和硬件描述语言。因为现代复杂数字逻辑系统的设计都是借助于EDA 工具完成的，无论电路系统的仿真和综合都需要掌握硬件描述语言。在本书中我们将要比较详细地介绍Verilog 硬件描述语言。-Programmers to take advantage of a design by the experts can either be understood algorithmic problem solving process can also be explained by the computer language to represent. This language is a programming language. By it expressed algorithmic problem solving process is the program. We are already familiar with to solve computational problems by writing programs in C, Pascal, Fortran, Basic or assembly language language several common programming languages. If we only study the algorithm, running on a general purpose computer program to design a dedicated microprocessor embedded systems or the use of general-purpose CPU master the above language is sufficient. If you need to design and manufacturing for quick calculation of the hard-wired logic circuit, we must learn the basic knowledge of digital circuit hardware description language. Because the design of the modern complex digital logic systems are accomplished by means of EDA tools, regardless of the circuit system simulation a
Date : 2025-07-06 Size : 1.28mb User : exia_dl
[Software Engineering] CPU-implementation-in-verilog DL : 0: 用verilogHDL实现CPU各项功能-The implementation of CPU funtions based on verilogHDL
Date : 2025-07-06 Size : 403kb User : yuxin tan
[Other] CPU DL : 0: 流水线简单CPU设计，基于简单的数字系统设计，为verilog语言，电路设计基于基本的数字电路-Pipelined CPU design, design of digital system based on a simple, Verilog language, based on the basic digital circuit design
Date : 2025-07-06 Size : 286kb User : 邹楠
[VHDL-FPGA-Verilog] RISC-CPU DL : 1: 精简指令集RISC-CPU 可以实现阶乘运算 verilog代码编写含有测试平台-Reduced instruction set RISC-CPU test platform can implement written in the factorial operator verilog code contains
Date : 2025-07-06 Size : 3.14mb User :
[VHDL-FPGA-Verilog] System-Verilog-and-HDL-skills DL : 1: 这个教程讲了如何用SystemVerilog写一个CPU，这个教程是和视频专辑http://i.youku.com/u/UMTExNzExOTgw/videos一起使用的，而且里面讲了一些FPGA的逻辑设计技巧-This tutorial about how to use SystemVerilog write a CPU, this tutorial is used in conjunction with, and the video album http://i.youku.com/u/UMTExNzExOTgw/videos and tells about some of FPGA logic design techniques
Date : 2025-07-06 Size : 3.04mb User : 易瑜
[VHDL-FPGA-Verilog] cpu DL : 0: 用system verilog写的一个arm处理器原代码。-Write an ARM processor system verilog source code.
Date : 2025-07-06 Size : 3.08mb User : 张力
[VHDL-FPGA-Verilog] RISC-CPU DL : 1: 精简指令集 CPU 通过仿真验证正确 (使用之前务必看readme文件，和结构图!) 1. 此cpu是夏宇闻 verilog数字系统设计教程中最后一章的例程。 2. 学习时务必先搞明白框图原理，和数据流动！！！ 3. 牢记主状态机中一条指令周期中传输的16bit=3bit指令+13bit地址。 4. 理解数据总线，和地址总线。区分数据和地址。 5. 仔细调试，因为书中有很多小错误。程序经过quartusii编译通过，另外经过modelsim仿真正确。-RISC CPU properly verified by simulation (using the previously sure to see the readme file and structure chart!) This CPU is the last chapter Xia Wen verilog Digital System Design Guide routine. 2 study sure to thoroughly understand block diagram of the principle, and the flow of data! ! ! Keep in mind one instruction cycle in the transmission of the main state machine the 16bit = 3bit instruction+13bit address. 4 understand the data bus and address bus. Between data and addresses. Carefully debugging, because there are many small errors in the book. The program compiled through quartusii by the addition after modelsim simulation.
Date : 2025-07-06 Size : 4.14mb User : 刘栋
[Software Engineering] lab-1-ALU-design-with-Verilog-HDL DL : 0: cpu设计的运算器部分verilog代码，实验资料，包括原理和代码，在modelsim仿真通过-CPU design arithmetic unit part of the verilog code, experimental data, including the principle and code, through the modelsim simulation
Date : 2025-07-06 Size : 19kb User : 张明明
[Software Engineering] lab-4-cpu-design-with-Verilog-HDL DL : 0: 用veriloghdl 编写的cpu代码，modusim仿真通过，包括原理图和代码，以实验报告形式写出-CPU code, written in veriloghdl modusim simulation through, including the principle diagram and code, in the form of a lab report write
Date : 2025-07-06 Size : 22kb User : 张明明
[VHDL-FPGA-Verilog] CPU DL : 0: 东南大学VHDL课程CPU设计 Verilog语言-Southeast University, CPU design Verilog language VHDL course
Date : 2025-07-06 Size : 506kb User : yu
[Other] pipelined-CPU DL : 0: verilog实现的流水线CPU 通过仿真和下载验证-verilog achieve pipelined CPU verified by simulation and downloads
Date : 2025-07-06 Size : 7.27mb User : 黄晓颖

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